1. Field of the Invention
This invention relates to digital signal processing.
2. Description of the Prior Art
In a digital switching apparatus such as a digital audio mixer, when a switch (or "cut") is to occur from one digital audio signal to another, it is usual to apply the cut when the two signals are the same. Even though this leads to a delay between initiation and implementation of the cut, the requirement that both signals are the same reduces the magnitude of an audible "click" generated by the cut.
With a multibit PCM (pulse code modulated) audio signal, it is relatively straightforward to detect when the two signals are the same, simply by comparing the numerical values of corresponding PCM samples for the two signals.
For one-bit digital audio signals, an appropriate test is that the two one-bit signals are the same over a number of corresponding successive bits. However, if the requirement is that m bits are identical in the two signals, then statistically there will be an average delay of 2.sup.m samples before this will occur. For example, if the requirement is that 14 bits are to be identical the average delay before this will next occur is about 5 milliseconds in a 64 fs system.sup.1. However, this delay period is not bounded. FNT 1 Here, fs refers to an sampling rate of, for example, 44.1 kHz or 48 kHz. The one-bit digital audio signal in this example has a bit rate of 64 fs, or 2.8224 or 3.072 MHz rectively.
So, this leads to two conflicting requirements for deciding when to implement a cut between the two signals. Although it is better to wait for a large number of corresponding bits in the two signals to be identical before implementing the cut, it is undesirable to impose a long delay after the cut control is operated before the cut takes effect.
Similar problems can occur when two one-bit audio signals having separate clocking sources are being processed by a single piece of equipment, it is normal that the two clocks will have slightly different frequencies, within the tolerances defined by the formats of the digital signals. This means that clocking differences (expressed in numbers of bits or numbers of clock cycles) will tend to build up between the two signals.
A certain number of such errors can be handled by an input buffer, but of course a buffer has only a limited size. So, the normal way of dealing with such errors is to drop or repeat samples from the input signal. This process is generally known as "clock slipping".
In order to reduce the audible effect of clock slipping, it is better to drop or repeat a sample when the input signal and itself displaced by the number of dropped or repeated samples are substantially identical over a number of consecutive samples.
For one-bit signals, if the requirement is that m bits are identical between the signal and the displaced signal, then statistically there will be an average delay of 2.sup.m samples before this will occur. For example, if the requirement is that 14 bits are to be identical the average delay before this will next occur is about 5 milliseconds in a 64 fs system.
During this time delay (which is not bounded) further clocking errors could build up to the extent that the buffer capacity can be exceeded. However, if a very relaxed criterion is used to give a quicker response (e.g. a requirement that only a few bits must be identical) then the clock slipping operation can produce subjectively disturbing sounds (e.g. clicks) when samples are dropped or repeated.